Projects

2-GSPS 8-bit Asynchronous Time-Interleaved Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) for MM-wave Radar and Wideband Communication Applications

The aim of the project is to develop a high-speed (2-MSPS) 8-bit asynchronous time-interleaved successive approximation register (SAR) analog-to-digital-converter (ADC) for mm-wave radar and wideband communication systems such as WiGig and 5G. The proposed ADC will have 8 sub-ADC channels for time-interleaving to operate at 2 GSPS high sampling rate, will also use offset, linearity and clock skew calibration techniques to improve the overall performance of the ADC. The proposed SAR ADC will consume low power (20mW), will have high energy efficiency (77 fJ/conv-step) and will occupy small chip area (0.5 mm2) due to newly developed full custom SAR control unit and will be fabricated in 65 nm CMOS process technology.

Wideband Low Noise X-to-K Band SiGe BiCMOS T/R Module Core-Chip

Next generation phased arrays require new specifications with the improvements in the technology, that are enabling multi-functionality and multi-band operation to be capable of multi-beam formation at various frequencies for applications. Wideband operation is one of the main requirements of the new generation systems in single-beam operations and electronic warfare applications to form multi-purpose systems; single band designs can be replaced with a single multi-band chip, which presents cheaper solutions for space-satellite applications, 5G and beyond communication and military based radars. The project proposes a X-to-K band T/R module core-chip to satisfy the system requirements as following; Compact size multi band low power dissipation, low receiver NF, high phase (delay)/ amplitude resolution and high transmitter output power. Although III-V technologies satisfy the RF specifications, they are contradicting with the compactness and low-cost expectations which prevents them from broadening its market to commercial applications. In this project, a novel SiGe BiCMOS T/R core-chip is proposed, which targets system and circuit level solutions on the described content. The corechip is going to include basic sub-blocks in a half-duplex array with All-RF architecture.

Low-Noise High Linearity Amplifiers for 5G MassMIMO and Low-Noise mm-wave 5G Amplifiers

5G applications have pushed for higher data rate requirements with each new generation. The demand for increased data rates has not only increased expectations of the noise performance of LNA but also created a demand for increased communication distances which have attracted attention to massive multiple-input-multiple-output (MIMO) systems. MIMO systems have introduced a new challenge for modern receiver chains, an increased linearity requirement since a stronger interferer resistance is required with each new channel in the 5G frequency regions. In this project, the design of high-linearity low-noise amplifiers is aimed. The project focuses on the design of an LNA for the Sub-6 GHz bands of the 5G communication systems and another LNA for the 5G bands in the frequency range of 24-30 GHz.

• Funding Agency:

  Analog Devices Inc.